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dual, bootstrapped, 12 v mosfet driver with output disable ADP3650 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features all-in-one synchronous buck driver bootstrapped high-side drive one pwm signal generates both drives anti-crossconduction protection circuitry od for disabling the driver outputs applications telecom and datacom networking industrial and medical systems point of load conversion: memory, dsp, fpga, asic general description the ADP3650 is a dual, high voltage mosfet driver optimized for driving two n-channel mosfets, the two switches in a nonisolated synchronous buck power converter. each driver is capable of driving a 3000 pf load with a 45 ns propagation delay and a 25 ns transition time. one of the drivers can be boot- strapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. the ADP3650 includes overlapping drive protection to prevent shoot-through current in the external mosfets. the od pin shuts off both the high-side and the low-side mosfets to prevent rapid output capacitor discharge during system shutdown. the ADP3650 is specified over the temperature range of ?40c to +85c and is available in 8-lead soic_n and 8-lead lfcsp_vd packages. functional block diagram 2 3 od in ADP3650 vcc bst drvh sw drvl pgnd delay vcc 6 delay cmp cmp 1v 4 1 7 control logic 6 5 8 r bst r g c bst1 d1 c bst2 12 v q1 to inductor q2 r1 latch r2 q s 0 7826-001 figure 1.
ADP3650 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 low-side driver ............................................................................9 high-side driver ...........................................................................9 overlap protection circuit ...........................................................9 applications information .............................................................. 10 supply capacitor selection ....................................................... 10 bootstrap circuit ........................................................................ 10 mosfet selection ..................................................................... 10 high-side (control) mosfets ................................................ 10 low-side (synchronous) mosfets ........................................ 11 pcb layout considerations ...................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 7/10rev. 0 to rev. a changes to general description section ...................................... 1 changes to table 1 ............................................................................ 3 changes to operating ambient temperature range parameter, table 2 ................................................................................................ 5 changes to figure 8 and figure 9 ................................................... 7 changes to ordering guide .......................................................... 12 10/08revision 0: initial version
ADP3650 rev. a | page 3 of 12 specifications vcc = 12 v, bst = 4 v to 26 v, t a = ?40c to +85c, unless otherwise noted. 1 table 1. parameter symbol test conditions/comments min typ max unit digital inputs (in, od ) input voltage high 2.0 v input voltage low 0.8 v input current ?1 +1 a hysteresis 40 250 350 mv high-side driver output resistance, sourcing current bst ? sw = 12 v; t a = 25c 3.3 bst ? sw = 12 v; t a = ?40c to +85c 2.5 3.9 output resistance, sinking current bst ? sw = 12 v; t a = 25c 1.8 bst ? sw = 12 v; t a = ?40c to +85c 1.4 2.6 output resistance, unbiased bst ? sw = 0 v 10 k transition times t rdrvh bst ? sw = 12 v, c load = 3 nf, see figure 3 25 40 ns t fdrvh bst ? sw = 12 v, c load = 3 nf, see figure 3 20 30 ns propagation delay times t pdhdrvh bst ? sw = 12 v, c load = 3 nf, 32 45 70 ns 25c t a 85c, see figure 3 t pdldrvh bst ? sw = 12 v, c load = 3 nf, see figure 3 25 35 ns od pdl t see figure 2 20 35 ns od pdh t see figure 2 40 55 ns sw pull-down resistance sw to pgnd 10 k low-side driver output resistance, sourcing current t a = 25c 3.3 t a = ?40c to +85c 2.4 3.9 output resistance, sinking current t a = 25c 1.8 t a = ?40c to +85c 1.4 2.6 output resistance, unbiased vcc = pgnd 10 k transition times t rdrvl c load = 3 nf, see figure 3 20 35 ns t fdrvl c load = 3 nf, see figure 3 16 30 ns propagation delay times t pdhdrvl c load = 3 nf, see figure 3 12 35 ns t pdldrvl c load = 3 nf, see figure 3 30 45 ns od pdl t see figure 2 20 35 ns od pdh t see figure 2 110 190 ns timeout delay sw = 5 v 110 190 ns sw = pgnd 95 150 ns supply supply voltage range v cc 4.15 13.2 v supply current i sys bst = 12 v, in = 0 v 2 5 ma uvlo voltage v cc rising 1.5 3.0 v hysteresis 350 mv 1 all limits at temperature extremes are gua ranteed via correlation using standard st atistical quality control (sqc) methods.
ADP3650 rev. a | page 4 of 12 timing characteristics timing is referenced to the 90% and 10% points, unless otherwise noted. t pdlod 90% 10% od drvh or drvl t pdhod 0 7826-004 figure 2. output di sable timing diagram in drvh to sw drvl sw v th v th 1v t pdldrvl t fdrvl t pdldrvh t rdrvl t fdrvh t pdhdrvh t rdrvh t pdhdrvl 07826-005 figure 3. timing diagram
ADP3650 rev. a | page 5 of 12 absolute maximum ratings all voltages are referenced to pgnd, unless otherwise noted. table 2. parameter rating vcc ?0.3 v to +15 v bst dc ?0.3 v to vcc + 15 v <200 ns ?0.3 v to +35 v bst to sw ?0.3 v to +15 v sw dc ?5 v to +15 v <200 ns ?10 v to +25 v drvh dc sw ? 0.3 v to bst + 0.3 v <200 ns sw ? 2 v to bst + 0.3 v drvl dc ?0.3 v to vcc + 0.3 v <200 ns ?2 v to vcc + 0.3 v in, od ?0.3 v to +6.5 v operating ambient temperature range ?40c to +85c junction temperature range 0c to 150c storage temperature range ?65c to +150c lead temperature soldering (10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 8-lead soic_n (r-8) 2-layer board 123 c/w 4-layer board 90 c/w 8-lead lfcsp_vd 1 (cp-8-2) 4-layer board 50 c/w 1 for lfcsp_vd, ja is measured per jedec std with exposed pad soldered to pcb. esd caution
ADP3650 rev. a | page 6 of 12 pin configurations and function descriptions od 1 in 2 bst 3 v cc 4 drvh 8 sw 7 pgnd 6 drvl 5 ADP3650 top view (not to scale) 07826-002 figure 4. 8-lead soic_n pin configuration pin 1 indicator 1 2 3 4 7 8 6 5 top view (not to scale) od bst vcc drvh notes 1. it is recommended that the exposed pad and the pgnd pin be connected on the pcb. sw pgnd drvl ADP3650 in 07826-003 figure 5. 8-lead lfcsp_vd pin configuration table 4. pin function descriptions pin o. nemonic description 1 bst upper mosfet floating bootstrap supply. a capacitor connected between the bst and sw pins holds this bootstrapped voltage for the high-sid e mosfet while it is switching. 2 in logic level pwm input. this pin has primary control of the drive outputs. in normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. 3 od output disable. when low, this pin disables normal operation, forcing drvh and drvl low. 4 vcc input supply. this pin should be bypassed to pgnd with an ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 pgnd power ground. this pin should be closely connected to the source of the lower mosfet. this pin is not internally connected to the exposed pad on the lfcsp. it is recommended that this pin and the exposed pad be connected on the pcb. 7 sw switch node connection. this pin is connected to the buck switching node, close to the upper mosfet source. it is the floating return for the upper mosfet drive sign al. it is also used to monitor the switched voltage to prevent the lower mosfet from turning on until the voltage is below ~1 v. 8 drvh buck drive. output drive for the upper (buck) mosfet. ep exposed pad for the lfcsp, the exposed pad and the pgnd pin shou ld be connected on the pcb. for more information about exposed pad packages, see the an-772 application note at www.analog.com .
ADP3650 rev. a | page 7 of 12 typical performance characteristics ch1 5v ch3 10v ch2 5v m40ns a ch1 2.4v 2 1 3 t 20.2% drvh in 07826-006 drvl figure 6. drvh rise and drvl fall times, c load = 6 nf for drvl, c load = 2 nf for drvh ch1 5v ch3 10v ch2 5v m40ns a ch1 2.4v 2 1 3 t 20.2% drvh in 07826-007 drvl figure 7. drvh fall and drvl rise times, c load = 6 nf for drvl, c load = 2 nf for drvh 28 26 24 22 20 18 14 ?40?30?20?100 10203040506070 80 junction temperature (c) rise time (ns) 16 07826-008 drvl drvh figure 8. drvh and drvl rise times vs. temperature 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 ?40?30?20?100 1020304050607080 junction temperature (c) fall time (ns) 07826-009 drvl drvh figure 9. drvh and drvl fall times vs. temperature 40 5 2.0 5.0 load capacitance (nf) rise time (ns) 35 30 25 20 15 10 2.5 3.0 3.5 4.0 4.5 t a = 25c vcc = 12v drvh drvl 07826-010 figure 10. drvh and drvl rise times vs. load capacitance 35 5 2.0 5.0 load capacitance (nf) fall time (ns) 30 25 20 15 10 2.5 3.0 3.5 4.0 4.5 vcc = 12v t a = 25c drvh drvl 07826-011 figure 11. drvh and drvl fall times vs. load capacitance
ADP3650 rev. a | page 8 of 12 60 0 0 frequency (khz) supply current (ma) 45 30 15 200 400 600 800 1000 1200 1400 t a = 25c vcc = 12v c load = 3nf 07826-012 figure 12. supply current vs. frequency 13 9 0 125 junction temperature (c) supply current (ma) 12 11 10 25 50 75 100 vcc = 12v c load = 3nf f in = 250khz 07826-013 figure 13. supply current vs. temperature 12 0 01 v cc (v) drvl output voltage (v) 2 11 10 9 8 7 6 5 4 3 2 1 1234567891011 t a = 25c c load = 3nf 07826-014 figure 14. drvl output voltage vs. supply voltage
ADP3650 rev. a | page 9 of 12 theory of operation the ADP3650 is optimized for driving two n-channel mosfets in a synchronous buck converter topology. a single pwm input (in) signal is all that is required to properly drive the high-side and the low-side mosfets. each driver is capable of driving a 3 nf load at speeds up to 500 khz. a functional block diagram of the ADP3650 is shown in figure 1 . low-side driver the low-side driver is designed to drive a ground referenced n-channel mosfet. the bias supply to the low-side driver is internally connected to the vcc supply and pgnd. when the driver is enabled, the driver output is 180 out of phase with the pwm input. when the ADP3650 is disabled, the low-side gate is held low. high-side driver the high-side driver is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by an external bootstrap supply circuit that is connected between the bst and sw pins. the bootstrap circuit comprises diode d1 and bootstrap capacitor c bst1 . c bst2 and r bst are included to reduce the high- side gate drive voltage and to limit the switch node slew rate. when the ADP3650 starts up, the sw pin is at ground, so the bootstrap capacitor charges up to v cc through d1. when the pwm input goes high, the high-side driver begins to turn on the high-side mosfet, q1, by pulling charge out of c bst1 and c bst2 . as q1 turns on, the sw pin rises up to v in and forces the bst pin to v in + v c (bst) . this holds q1 on because enough gate- to-source voltage is provided. to complete the cycle, q1 is switched off by pulling the gate down to the voltage at the sw pin. when the low-side mosfet, q2, turns on, the sw pin is pulled to ground. this allows the bootstrap capacitor to charge up to vcc again. the output of the high-side driver is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. overlap protection circuit the overlap protection circuit prevents both of the main power switches, q1 and q2, from being on at the same time. this is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. the overlap protection circuit accomplishes this by adaptively controlling the delay from the q1 turn-off to the q2 turn-on and by internally setting the delay from the q2 turn-off to the q1 turn-on. to prevent the overlap of the gate drives during the q1 turn-off and the q2 turn-on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 begins to turn off (after propagation delay). before q2 can turn on, the overlap protection circuit makes sure that sw has first gone high and then waits for the voltage at the sw pin to fall from v in to 1 v. when the voltage on the sw pin falls to 1 v, q2 begins to turn on. if the sw pin has not gone high first, the q2 turn-on is delayed by a fixed 150 ns. by waiting for the voltage on the sw pin to reach 1 v or for the fixed delay time, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. if sw does not go below 1 v after 190 ns, drvl turns on. this can occur if the current flowing in the output inductor is negative and flows through the high-side mosfet body diode.
ADP3650 rev. a | page 10 of 12 applications information supply capacitor selection for the supply input (vcc) of the ADP3650, a local bypass capacitor is recommended to reduce noise and to supply some of the peak currents that are drawn. use a 4.7 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the ADP3650. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a diode, as shown in figure 1 . these components can be selected after the high-side mosfet is chosen. the bootstrap capacitor must have a voltage rating that can handle twice the maximum supply voltage. a minimum 50 v rating is recom- mended. the capacitor values are determined by gate gate bst2 bst1 v q cc =+ 10 (1) d cc gate bst2 bst1 bst1 vv v cc c ? = + (2) where: q gate is the total gate charge of the high-side mosfet at v gate . v gate is the desired gate drive voltage (usually in the range of 5 v to 10 v, 7 v being typical). v d is the voltage drop across d1. rearranging equation 1 and equation 2 to solve for c bst1 yields vv q c d cc gate bst ? = 10 1 c bst2 can then be found by rearranging equation 1. 1 10 bst gate gate bst2 c v q c ?= for example, an ntd60n02 has a total gate charge of about 12 nc at v gate = 7 v. using v cc = 12 v and v d = 1 v, then c bst1 = 12 nf and c bst2 = 6.8 nf. good quality ceramic capacitors should be used. r bst is used to limit slew rate and minimize ringing at the switch node. it also provides peak current limiting through d1. an r bst value of 1.5 to 2.2 is a good choice. the resistor needs to handle at least 250 mw due to the peak currents that flow through it. a small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by v cc . the bootstrap diode must have a minimum 15 v rating to withstand the maximum supply voltage. the average forward current can be estimated by max gate avgf fqi = )( (3) where f max is the maximum switching frequency of the controller. the peak surge current rating should be calculated by bst d cc peakf r vv i ? = )( (4) mosfet selection when interfacing the ADP3650 to external mosfets, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the mosfets. these stresses include exceeding the short time duration voltage ratings on the driver pins as well as on the external mosfet. it is also highly recommended that the bootstrap circuit be used to improve the interaction of the driver with the characteristics of the mosfets (see the bootstrap circuit section). if a simple bootstrap arrangement is used, make sure to include a proper snubber network on the sw node. high-side (control) mosfets a high-side, high speed mosfet is usually selected to minimize switching losses. this typically implies a low gate resistance and low input capacitance/charge device. yet, a significant source lead inductance can also exist that depends mainly on the mosfet package; it is best to contact the mosfet vendor for this information. the ADP3650 drvh output impedance and the input resistance of the mosfets determine the rate of charge delivery to the internal capacitance of the gate. this determines the speed at which the mosfets turn on and off. however, because of potentially large currents flowing in the mosfets at the on and off times (this current is usually larger at turn-off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage when the high-side mosfets switch off. this creates a significant drain-source voltage spike across the internal die of the mosfets and can lead to a catastrophic avalanche. the mechanisms involved in this avalanche condition are referenced in literature from the mosfet suppliers.
ADP3650 rev. a | page 11 of 12 the mosfet vendor should provide a safe operating rating for maximum voltage slew rate at a given drain current. this allows the designer to derate for the fet turn-off condition described in this section. when this specification is obtained, determine the maximum current expected in the mosfet by () out max max out cc dc max lf d vvphaseperii ?+ = ) (( 5 ) where: d max is determined by the voltage controller being used with the driver. this current is divided roughly equally between mosfets if more than one is used (assume a worst-case mismatch of 30% for design margin). l out is the output inductor value. when producing the design, there is no exact method for calculating the dv/dt due to the parasitic effects in the external mosfets as well as in the pcb. however, it can be measured to determine whether it is safe. if it appears that the dv/dt is too fast, an optional gate resistor can be added between drvh and the high-side mosfets. this resistor slows down the dv/dt, but it increases the switching losses in the high-side mosfets. the ADP3650 is optimally designed with an internal drive impedance that works with most mosfets to switch them efficiently, yet minimizes dv/dt. however, some high speed mosfets may require this external gate resistor depending on the currents being switched in the mosfet. low-side (synchronous) mosfets the low-side mosfets are usually selected to have a low on resistance to minimize conduction losses. this usually implies a large input gate capacitance and gate charge. the first concern is to make sure that the power delivery from the ADP3650 drvl does not exceed the thermal rating of the driver. the next concern for the low-side mosfets is to prevent them from being inadvertently switched on when the high-side mosfet turns on. this occurs due to the drain-gate capacitance (miller capacitance, also specified as c rss ) of the mosfet. when the drain of the low-side mosfet is switched to vcc by the high-side mosfet turning on (at a dv/dt rate), the internal gate of the low-side mosfet is pulled up by an amount roughly equal to v cc (c rss /c iss ). it is important to make sure that this does not put the mosfet into conduction. another consideration is the nonoverlap circuitry of the ADP3650 that attempts to minimize the nonoverlap period. during the state of the high-side mosfet turning off to the low-side mosfet turning on, the sw pin is monitored (as well as the conditions of sw prior to switching) to adequately prevent overlap. however, during the low-side turn-off to high-side turn-on, the sw pin does not contain information for determining the proper switching time, so the state of the drvl pin is monitored to go below one-sixth of v cc ; then, a delay is added. due to the miller capacitance and internal delays of the low- side mosfet gate, ensure that the miller-to-input capacitance ratio is low enough, and that the low-side mosfet internal delays are not so large as to allow accidental turn-on of the low-side mosfet when the high-side mosfet turns on. p cb layout considerations u se the following general guidelines when designing printed circuit boards. figure 15 shows an example of the typical land patterns based on these guidelines. ? trace out the high current paths and use short, wide (>20 mil) traces to make these connections. ? minimize trace inductance between the drvh and drvl outputs and the mosfet gates. ? connect the pgnd pin of the ADP3650 as close as possible to the source of the lower mosfet. ? locate the vcc bypass capacitor as close as possible to the vcc and pgnd pins. ? when possible, use vias to other layers to maximize thermal conduction away from the ic. d1 c bst2 c bst1 r bst c vcc 07826-015 figure 15. external component placement example
ADP3650 rev. a | page 12 of 12 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 16. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) 0 90308-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 17. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm x 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity branding ADP3650jrz ?40c to +85c 8-lead standard small outline package (soic_n) r-8 98 ADP3650jrz-rl ?40c to +85c 8-lead standard small outline package (soic_n) r-8 2,500 ADP3650jcpz-rl ?40c to +85c 8-lead lead frame chip scale package (lfcsp_vd) cp-8-2 5,000 l91 1 z = rohs compliant part. ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07826-0-7/10(a)

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